This invention pertains to the measurement of sense amplifier offset voltages in a static random access memory (hereinafter referred to as an "SRAM"). More particularly, this invention pertains to methods and apparatus which allow an engineer to gather precise statistical data on the offset voltage characteristics of sense amplifiers used in a particular SRAM design or fabrication process. The statistical data can then be used for purposes such as 1) increasing the speed of an SRAM, or 2) decreasing the size of an SRAM.
The accurate measurement of sense amplifier offset voltages is a very important factor in generating a timing budget for an SRAM. On one hand, enough time must be allotted during each clock cycle of SRAM operation to guarantee that the bit lines driven by each random access memory cell (hereinafter referred to as a "RAM cell") develop sufficient differential voltage to overcome the offset voltages of the sense amplifiers to which they are connected. On the other hand, it is undesirable to allot any more time for bit line charging than is necessary, since an SRAM's operating speed is directly and adversely impacted by time allotted to developing excess differential voltages across bit lines.
It is therefore desirable to accurately determine sense amplifier offset voltages so that an SRAM's timing budget allows "just enough" time for its RAM cells to charge their associated bit lines.
In the past, the offset voltages of sense amplifiers contained in a production SRAM have been difficult to measure. When measured, offset voltages have been obtained through the manufacture of special SRAM prototypes with added testability features. Since this is an expensive and time consuming process, mathematical models of an SRAM are often used to estimate the offset voltages of an SRAM's sense amplifiers.
Modeling has several disadvantages. First, there are some characteristics of an SRAM that cannot be accurately modeled. The offset voltage and drain current of a field effect transistor (fet) are two such characteristics. These characteristics are the two most fundamental quantities used in fet modeling, and their interaction as a fet is just beginning to turn on is very important to the modeling of a sense amplifier. Unfortunately, mathematical models are often based on generalized or inappropriate process data, such as the use of vertically packaged fets rather than horizontally packaged fets. Although such a modeling inaccuracy might appear negligible, it could translate into a relatively large error when it comes to predicting a sense amplifier's rather small offset voltage.
Second, and in order to account for modeling inaccuracies, the SRAM timing budget produced by modeling must be conservative. Failure to allot enough time for bit line charging can result in loss of data or data errors.
It is therefore a primary object of this invention to provide methods and apparatus for accurately measuring the offset voltages of each and every sense amplifier in an SRAM (or alternatively, a subset of sense amplifiers within an SRAM).
It is a further object of this invention to provide methods and apparatus which do not detrimentally effect the normal operation of an SRAM.
It is yet another object of this invention to provide methods and apparatus which provide statistically significant offset voltage data for a specific SRAM design or fabrication process, thereby enabling the creation of SRAM timing budgets which allot "just enough" time for bit line charging and the overcoming of sense amplifier offset voltages.